1. Field of the Invention
The present invention relates generally to a semiconductor device and fabrication method thereof, and more specifically, to a fabricating method of etching a high-k dielectric layer having a U-shape profile and the semiconductor device fabricated thereby.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect, which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals that are suitable for use as the high-K gate dielectric layer are used to replace the conventional poly-silicon gate to be the control electrode.
In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well known that compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the anneal process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. After performing the anneal process having such strict heat budget, it is found that a flat band voltage (Vfb) does not increase or decrease linearly with decreasing EOT of the high-K gate dielectric layer. Instead, a roll-off issue is observed. Therefore, the gate last process is developed to improve the Vfb roll-off issue and avoid generating leakage current due to re-crystallization of the high-K gate dielectric layer occurring in high-temperature processes, and to widen material choices for the high-K gate dielectric layer and the metal gate in the gate first process.
In the conventional gate last process, a sacrifice gate or a replacement gate is provided and followed by performing processes used to construct a normal MOS transistor. Then, the sacrifice/replacement gate is removed to form a trench. Consequently, the structure formed by a gate-last process (more specifically to being formed by a gate-last for high-k last process) would have a high-k dielectric layer having a U-shape profile 110, a work function metal layer having a U-shape profile 120, and further comprises a plurality of barrier layers 130 formed between each layer as shown in FIG. 1. These multiple layers having a U-shape profile would lead to a protruding structure 150 at the top portion of the trench 140, therefore reducing the opening of the trench 140. As the size of the semiconductor device shrinks, the sequential formed a filling metal layer (not shown), aluminum for example, will be difficult to be filled into the trench 140. Otherwise, the fringe capacitance of the semiconductor device 100 increases because of the high-k dielectric layer having a U-shape profile 110, therefore reducing the electrical performance of the semiconductor device.